1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a circuit structure for controlling a test operation of a dynamic semiconductor memory device.
2. Description of the Background Art
FIG. 17 schematically shows a whole structure of a dynamic semiconductor memory device in the prior art. In FIG. 17, a semiconductor memory device 1 includes four memory cell planes 2a-2d, which are formed on a semiconductor chip and each has a plurality of memory cells arranged in a matrix form.
In order to select a memory cell in accordance with an address signal, there are arranged a row select circuit (a row predecoder, a row decoder and a word line driver) and a column select circuit (a column predecoder, a column decoder and an I/O gate), which are not shown for simplifying the figure.
Each of memory cell planes 2a-2d is divided into four column groups. A global I/O line pair GIOP is arranged for each column group. When one of memory cell planes 2a-2d is selected, the memory cell of one bit is selected in each of the column groups in the selected memory cell plane, and is coupled to global I/O line pair GIOP for the selected memory cell.
The semiconductor memory device further includes preamplifier/write-buffers 7, which are provided correspondingly to global I/O line pairs GIOP for input/output of data to and from corresponding global I/O line pairs GIOP, respectively, read drivers 8, which amplify internal read data sent from the corresponding preamplifiers and send the same to the corresponding read data buses RDAP (RDAPa-RDAPd), respectively, first test mode circuits 9, which are provided correspondingly to memory cell planes 2a-2d, respectively, and determine match/mismatch of logics of data read from preamplifier/write-buffers 7 in a test operation mode, a second test mode circuit 10, which receives signals indicative of results of determination sent from first test mode circuits 9 provided for memory cell planes 2a-2d, respectively, and determines match/mismatch of logics of the determination result signals thus received, and a driver circuit 11 which receives signals on read data buses RDAPa-RDAPd and a signal sent from test mode circuit 10, and selectively transmits the received signals to an output buffer 13 via an output bus RDP.
Preamplifier/write-buffers 7 select one of the four column groups in each of memory cell planes 2a-2d, and the memory cell data in the selected column group is transmitted via read driver 8 onto the corresponding one of read data buses RDAPa-RDAPd.
In the test operation mode, all the four column groups are selected in each of memory cell planes 2a-2d, and the output signals of four preamplifiers 7 are transmitted to corresponding first test mode circuit 9.
In the normal operation mode, driver circuit 11 selects data read from the selected memory cell plate among data read onto read data buses RDAPa-RDAPd, and send the same to output buffer 13.
In the test operation mode, driver circuit 11 selects the signal indicative of the test result sent from test mode circuit 10, and transmits the same via output data bus RDP to output buffer 13.
Write buffers of preamplifier/write-buffers 7 are coupled to an input buffer 12 via an input data bus WD. Write buffers 7 corresponding to the selected one among memory cell planes 2a-2d are activated, and data is written via the write buffer into selected memory cells contained in the selected column group in the selected memory cell plane.
The semiconductor memory device further includes an address buffer 3 which receives an externally applied address signal and produces an internal address signal, an ATD generating circuit 4 which detects change in the internal address signal (internal column address signal) sent from address buffer 3 and generates an address change detection signal ATD, a PAE generating circuit 5 which is responsive to address change detection signal ATD sent from ATD generating circuit 4 to generate a preamplifier enable signal PAE for activating the preamplifier of preamplifier/write-buffer 7, and an IOEQ generating circuit 6 which is responsive to address change detection signal ATD sent from ATD generating circuit 4 and generates an equalize instruction signal IOEQ for equalizing global I/O line pair GIOP.
Global I/O line pair GIOP is formed of a pair of complementary signal lines for transmitting data signals which are complementary to each other. Equalize signal IOEQ functions to equalize the potentials on global I/O lines of global I/O line pair GIOP.
The semiconductor memory device further includes an internal voltage regulator 29, which receives an externally applied power supply potential Vcc, and generates a power supply potential Vccp for a peripheral circuit and a power supply potential Vccs for the memory cell plane, which are lower than external power supply potential Vcc. Power supply potential Vccp for peripheral circuit is supplied as an operation power supply potential to preamplifier/write-buffers 7, read drivers 8 and others.
Power supply potential Vccs for memory cell plane is applied to circuits for driving memory cell planes 2a-2d (i.e., sense amplifiers for charging/discharging bit lines) and substrate regions of p-channel MOS transistors in the planes.
Output buffer 13 and input buffer 12 perform external input/output of data via a common data input terminal DQ.
A multibit test operation related to the invention will be described below.
As a storage capacity of the semiconductor memory device increases, the number of memory cells increases. If determination of defect/nondefect in memory cells is performed bit by bit, an extremely long test time is required, resulting in increase in cost of chips. Therefore, determination of defect/nondefect is performed on multiple memory cells at a time, so that the test time can be reduced. This manner of performing the test on multiple memory cells at a time is called a multibit test mode.
An operation of writing test data in the multibit test mode will be described below. In each of memory cell planes 2a-2d, one memory cell row is selected. Then, in each of memory cell planes 2a-2d, memory cells of 4 bits are selected from memory cells belonging to the selected memory cell row. Test data to be written into the selected memory cells is transmitted to the write buffers in preamplifier/write-buffers 7 from input buffer 12.
In the multibit test mode, all the write buffers are enabled. Thereby, the same test data is written into the selected memory cells of 4 bits in each of memory cell planes 2a-2d, and thus the same test data is written into the memory cells of 16 bits in total.
Then, data reading in the multibit test mode will be described below.
Similarly to the test data writing, memory cells of 4 bits are simultaneously selected in each of memory cell planes 2a-2d. All the preamplifiers included in preamplifier/write-buffers 7 are enabled. Data of 4-bit memory cells selected in each of memory cell planes 2a-2d is amplified by the preamplifiers, and is transmitted to corresponding first test mode circuits 9.
Each first test mode circuit 9 determines match/mismatch of logics of received memory cell data of 4 bits, and sends a signal indicative of the result of determination to second test mode circuit 10.
Second test mode circuit 10 operates in accordance with the determination results sent from four first test mode circuits 9, and determines whether match of logics of test data read from four first test mode circuits 9 is detected or not.
The determination data issued from test mode circuit 10 is applied to output buffer 13 via driver 11, and output buffer 13 transmits this determination data to data I/O terminal DQ.
Thus, second test mode circuit 10 determines match/mismatch of logics of all the data of memory cell groups each including the memory cells of 4 bits selected in each of memory cell planes 2a-2d, i.e., all the data of memory cells of 16 bits in total. Based on the determination data sent from second test mode circuit 10, it is determined whether a defective memory cell is present among the simultaneously selected memory cells of 16 bits.
As described above, memory cells of 16 bits can be tested at a time, the test time can be significantly reduced.
In the conventional structure of the semiconductor memory device, the first test mode circuits are provided for the plurality of memory cell planes, respectively, and the output signals of these first test mode circuits are transmitted to the second test mode circuit, so that the second test mode circuit determines defect/nondefect of simultaneously selected memory cells.
In the above structures of the test mode circuits, however, it is impossible to specify the defective memory cell among the selected memory cells.
For example, in semiconductor memory devices having increased storage capacities, when a defective memory cell was found by the test, a memory cell column containing the defective memory cell is replaced with a backup or spare memory cell column. This replacement can prevent a malfunction, even when the defective memory cell was found.
In the multibit test of the semiconductor memory device in the prior art, however, the replacement with the spare memory cell column is impossible, because it is difficult to specify the memory cell column containing the defective memory cell. When an operation test was performed in the multibit test mode for reducing a test time, such a problem arises that a malfunction by the defective memory cell cannot be overcome.